1. Field of the Invention
The present invention relates to a cache controller that controls a cache attached to each processor in a multiprocessor system.
2. Description of the Related Art
In recent years, a parallel processing system using a plurality of processors, a so-called multiprocessor system, has been adopted to data processors such as computers to enhance throughput thereof.
However, as the scale of multiprocessor systems becomes larger, latency of data access to main memories is further prolonged, making it difficult to enhance throughput. The latency partly depends on the construction of the network connecting the processors and main memories. Accordingly, the prior art devised and attached a cache to each processor to shorten the latency. Once a cache miss happens, however, the processor requesting access to the main memories is left idle until the needed data is loaded into the cache, and thus a reduced processing speed also makes it difficult to enhance throughput.
Given these circumstances, multithreading processing was proposed as an architecture that can enhance throughput by hiding the latency. An example is described in "Proceedings of the 17th Annual International Symposium on Computer Architecture", IEEE, pp. 104-114, 1990.
According to this type of processing, each processor suspends an ongoing execution of a thread (a unit of a program per execution, or namely an instruction stream) when a cache miss happens, and starts an execution of another thread while requesting data access to the main memories. By doing so, the processor can enhance throughput with a continuous operation. Such enhancement is limited when conventional caches are used in a uniprocessor or the multiprocessor system. Because of these caches, it unavoidably takes a certain time to resume the execution of the once-suspended thread since the data has been loaded into the cache. A cache miss thus may happen again if another thread has replaced a block (a set of data in 64-128 bytes) containing the data with another during that certain time, thereby decreasing an overall processing speed. Yet, neither a construction nor a controlling method of a cache suitable for the multithreading processing has been disclosed to date.